A FPGA Stereo Matching Algorithm Modeled By DSP Builder

This paper proposes a System-on-ProgrammableChip (SoPC) architecture to implement a stereo matching algorithm based on the sum of absolute differences (SAD) in a FPGA chip which can provide 1396×1110 disparity maps at 30 fps speed. The hardware implementation involves a 32bit Nios II microprocessor, memory interfaces and stereo matching algorithm circuit module. The stereo matching algorithm core is modeled by the Matlab-based DSP Builder. The system can process many different sizes of stereo pair images through a configuration interface. The maximum horizon resolution of stereo images is 2048.